Switching speed measurement is a critical dynamic characterization test that determines how quickly new power semiconductor devices—such as SiC MOSFETs, GaN HEMTs, and advanced IGBTs—transition between on and off states. Accurate measurement of turn-on/turn-off times, rise/fall times, dv/dt, di/dt, and switching energy losses directly influences converter efficiency, thermal design, and EMI performance. This article explains the principles, sample types, test items, measurement methods, applicable standards, and common questions related to switching speed determination for next-generation power devices.
Technical Overview
Switching speed measurement quantifies the dynamic transition behavior of a semiconductor device as it moves between the blocking state and the conducting state. For new-generation power devices—particularly wide-bandgap (WBG) semiconductors such as silicon carbide (SiC) and gallium nitride (GaN)—switching transitions occur in the nanosecond or even sub-nanosecond range, far faster than conventional silicon MOSFETs and IGBTs. This extreme speed delivers lower switching losses, higher operating frequency, and greater power density, but it also introduces significant measurement challenges.
The core parameters of interest include turn-on delay time, rise time, turn-off delay time, fall time, voltage slew rate (dv/dt), current slew rate (di/dt), and the associated switching energy losses (Eon, Eoff). Because WBG devices generate transient voltages and currents with steep edges, measurement setups must minimize parasitic inductance and capacitance, and instrumentation must offer sufficient analog bandwidth to avoid waveform distortion. Reliable switching speed data is essential for device datasheets, gate-driver design, converter loss modeling, and qualification of devices against international standards such as IEC 60747 and JEDEC guidelines.
Testing Samples
Silicon Power Discrete Devices
Conventional silicon-based devices remain widely tested to establish baseline dynamic performance and to verify improvements offered by new device technologies. Typical samples include:
- Silicon MOSFETs (low-, mid-, and high-voltage classes)
- Insulated-gate bipolar transistors (IGBTs), including trench-field-stop generations
- Fast-recovery and ultrafast-recovery diodes
- Schottky barrier diodes and silicon-based power bipolar transistors
Wide-Bandgap Devices
SiC and GaN devices are the primary focus of new device switching speed evaluation due to their exceptionally fast transitions:
- SiC MOSFETs (discrete and bare dies), SiC cascode devices
- SiC merged PiN Schottky (MPS) diodes and SiC Schottky barrier diodes
- GaN high-electron-mobility transistors (HEMTs), both enhancement-mode and cascode configurations
- GaN power stage ICs with integrated drivers
Power Modules and Assemblies
Multi-chip packages, half-bridge and six-pack power modules, intelligent power modules (IPMs), and custom converter sub-assemblies are tested to evaluate how packaging parasitics, bond wires, and layout affect achievable switching speed in real applications.
Testing Items
Switching speed determination covers a comprehensive set of dynamic parameters, typically extracted under defined bus voltage, load current, gate resistance, and junction temperature conditions:
- Turn-on delay time (td(on)): interval from gate signal reaching a defined threshold to drain current beginning to rise
- Rise time (tr): time for drain current to rise from 10% to 90% of the load current, or for drain-source voltage to fall through the corresponding levels
- Turn-on time (ton): sum of turn-on delay time and current rise/voltage fall intervals
- Turn-off delay time (td(off)): interval from gate signal removal to current beginning to fall
- Fall time (tf): time for current to fall or voltage to rise between defined percentage levels
- Turn-off time (toff): sum of turn-off delay time and fall time
- Voltage slew rate (dv/dt) and current slew rate (di/dt) during switching transitions
- Turn-on energy loss (Eon) and turn-off energy loss (Eoff)
- Reverse recovery time (trr), reverse recovery charge (Qrr), and reverse recovery energy (Err) of body/parasitic or companion diodes
- Maximum practical switching frequency assessment and gate-drive sensitivity analysis
- Overshoot voltage, ringing frequency, and cross-over characteristics during hard switching
Testing Methods
Double Pulse Test (DPT)
The internationally recognized method for characterizing hard-switching behavior is the double pulse test, performed in accordance with JEDEC JEP183 (guideline for dynamic switching loss measurement of power devices), IEC 60747 series provisions, and related JEDEC JESD24 practices. The device under test is operated in a clamped inductive load circuit: the first gate pulse ramps the load current in an inductor to the target value, the gate is briefly turned off to capture the turn-off waveform, and a second pulse is applied to capture the turn-on transition including diode reverse recovery. Because the inductor current is essentially constant between pulses, both switching events are measured at precisely controlled, repeatable current levels.
Instrumentation and Setup
A high-performance measurement chain is required to capture fast WBG transitions accurately:
- High-bandwidth digital oscilloscope (typically 500 MHz to 1 GHz or higher for GaN devices)
- High-bandwidth current sensing: coaxial shunt resistors, current viewing resistors (CVR), or wideband Hall-effect/Rogowski probes selected to match the expected di/dt
- High-voltage passive or differential probes with adequate bandwidth and minimal capacitive loading
- Adjustable DC bus source, calibrated load inductor with low parasitic capacitance, and programmable gate driver with interchangeable gate resistances
- Temperature-controlled environment or heated fixture for evaluating switching behavior across the operating junction temperature range (commonly 25 °C to 150 °C or 175 °C)
Measurement Accuracy Practices
To ensure traceable and reproducible results, accredited third-party laboratories apply rigorous error-control procedures:
- Probe deskew calibration to align voltage and current channel propagation delays before energy loss integration
- Minimization of power loop and gate loop parasitic inductance through coaxial and Kelvin-connected layouts
- Verification of scope timing accuracy, bandwidth, and vertical resolution against calibration references
- Definition-consistent waveform extraction (10%/90% or 90%/10% crossover definitions) per IEC 60747 and JEDEC terminology
- Matrix testing across bus voltage, load current, gate resistance, and temperature to characterize switching speed dependency
Applications
Switching speed measurement data supports design and qualification decisions across the entire power electronics industry:
- Electric vehicle traction inverters, on-board chargers, and DC-DC converters, where SiC and GaN switching speed determines drive cycle efficiency and range
- Data center and server power supplies, where multi-level totem-pole PFC stages exploit fast GaN switching
- Solar string and micro-inverters, requiring high efficiency and high power density under wide load conditions
- Industrial motor drives and servo systems, where switching frequency and losses influence thermal design and acoustic performance
- Consumer fast chargers and adapters using high-frequency GaN power stages
- Railway traction, aerospace power systems, and grid-tied converters demanding verified dynamic performance under stringent reliability requirements
- Device manufacturer datasheet generation, incoming inspection, lot-to-lot quality monitoring, and technology benchmarking of new device platforms
FAQ
Why is switching speed especially important for new semiconductor devices?
Wide-bandgap devices achieve transition speeds many times faster than silicon, which reduces switching losses and enables higher operating frequencies. However, faster edges amplify the influence of parasitic inductance, increase voltage overshoot and EMI, and push measurement systems to their limits, making precise characterization indispensable.
What standards govern switching speed measurement?
Commonly referenced frameworks include the IEC 60747 series for discrete semiconductor device dynamic characteristics, JEDEC guidelines such as JEP183 for dynamic switching loss measurement of SiC power devices, JESD24 for MOSFET switching, and regional standards such as relevant GB/T and JIS documents for power semiconductor testing.
How is measurement uncertainty controlled?
Uncertainty is managed through deskew calibration between voltage and current channels, selection of probes with bandwidth matched to the transition speed, minimization of loop parasitics, and repeated measurements across statistically valid sample sizes. Accredited third-party laboratories follow documented calibration procedures traceable to national metrology references.
At what temperatures is switching speed tested?
Testing is typically performed at room temperature (25 °C) and at elevated junction temperatures up to the device rated maximum (commonly 125 °C to 175 °C), because switching speed and losses of many device technologies vary significantly with temperature.
Can soft-switching or resonant topologies also be evaluated?
Yes. Beyond the standard hard-switching double pulse test, custom fixtures can replicate zero-voltage or zero-current switching conditions to measure effective transition times and residual losses in resonant converter applications.
What deliverables are provided after testing?
A typical test report includes full switching waveform records, extracted timing parameters (delay, rise, and fall times), dv/dt and di/dt values, calculated switching energies, test condition matrices, and an uncertainty assessment, providing engineers with datasheet-grade dynamic characterization data.